Semiconductor controller device having a controlled output driver characteristic

ABSTRACT

An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block ( 120 ), an analog voltage divider ( 104 ), an input comparator ( 125 ), a sampling latch ( 130 ), a current control counter ( 115 ), and a bitwise output driver (output driver A  107  and output driver B  111 ).

[0001] This application claims priority to the provisional patentapplication entitled “Current Control Circuit”, Serial Number60/073,353, filed Feb. 2, 1998, and the provisional patent applicationentitled “Current Control Technique”, Serial No. 60/057,400, filed Aug.29, 1997.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to the field of integrated circuitsand high-speed buses. More specifically, the present invention relatesto a circuit for a high-speed driver and techniques for obtaining rapidswitching speed with low power consumption and low noise on high-speedbuses.

[0004] 2. Description of the Related Art

[0005] To obtain rapid switching speed on a bus with low powerconsumption and low noise, it is desirable for a current mode driver toset and control the current at which the driver operates. U.S. Pat. No.5,254,883, assigned to the assignee of the present invention, andincorporated herein by reference, discusses an apparatus and method forsetting and maintaining the operating current of a current mode driverfor a bus. Essentially, for a bus with a master-slave architecture,there are two problems to be solved in setting the operating current onthe bus. First, the operating current of the master's current modedrivers should be properly set. Second, the operating current of theslave's current mode drivers should be properly set. Once these currentsare set, they are maintained at those settings despite process, voltageand temperature variations by circuitry in the master and slave devices.

[0006] A master-slave bus architecture is discussed in the '883 patentin which a master may send data to and receive data from a slave. Aslave may send data to and receive data from a master, but not anotherslave. The master sets its operating current for its drivers and eachslave sets the operating current for its drivers.

[0007] The master employs an adjustable current sink as a driver foreach bus line that it drives. The current sink turns on to drive thevoltage on the bus line, V_(out), to a voltage closer to ground andturns off to allow a termination resistor, R_(term), on the bus line topull the bus line closer to the terminator voltage, V_(term). Thecurrent in the driver, I_(d), is set by a digital counter whose count isdetermined from a feedback circuit having a comparator. If the count isall zeros then no current flows in the driver and the voltage on the busline, V_(out), is the termination voltage, V_(term). If the count is allones, then the maximum current flows in the driver and the voltage onthe bus line, V_(out), equals V_(term)−I_(d)*R_(term).

[0008] The feedback circuit compares a voltage reference, V_(ref), to anode voltage, V_(n), derived from a scaled reference driver whichreceives the count from the counter. Feedback assures that the nodevoltage matches the reference voltage, V_(n)=V_(ref). When the matchoccurs the reference driver has an output swing (i.e., change involtage) of (V_(term)−V_(ref)) and the actual output driver has a swingof 2*(V_(term)−V_(ref)) due to the scaling between the reference driverand the actual output driver. Therefore, V_(out) equals(V_(term)−2)*(V_(term)−V_(ref)). Thus, by selecting a value for V_(term)and V_(ref) any size symmetric voltage swing about V_(ref) may beachieved.

[0009] The slave in the '883 patent also employs an adjustable currentsink as a driver for each bus line that it drives. A counter similarlycontrols the value of the current in the driver such that the driver mayswing between V_(term) and V_(term)−I_(d)*R_(term), where I_(d) is thecurrent setting in the driver of the slave. However, the value in thecounter is directly proportional to the value of an RC time constantwhose capacitance, C, is set by the master. The master also determineswhether the value of V_(out) from the driver matches V_(ref) in themaster. It adjusts the RC time constant so that the count in the counterwill set a current in the driver and V_(out) will match V_(ref). ThusV_(out) will equal V_(term)−(V_(term)−V_(ref)). In order to produce asymmetric swing about V_(ref) another step is required. The mastershould double the value of the RC time constant which will double thecount This will produce a V_(out) which is equal toV_(term)−2*(V_(term)−V_(ref)).

[0010] Maintenance of the current setting of the driver in the slave maybe performed in a manner different from that in the master. In theslave, the effective R in the RC time constant is derived from areference voltage and reference current. If due to variations intemperature or supply voltage, the reference current decreases then theeffective R in the RC time constant increases. This increases the countand the operational current setting of the driver in the slave, thuscompensating for the effect. If the reference current increases, theeffective R and the count decrease, again compensating for the change.

[0011] While the above techniques of setting and maintaining operatingcurrent in the master and slave bus line drives have met withsubstantial success, the techniques are not without certainshortcomings. For example, the technique of setting the current in themaster requires an extra pin dedicated to receive the external resistor.Another shortcoming is selecting the proper value of the externalresistor to maintain the factor of two scaling between (V_(term)−V_(n))and (V_(term)−V_(out)). If the scaling is not precisely set, the outputswing is not symmetric about V_(ref). Further, as process, voltage, ortemperature variations occur, the value selected for the resistor maynot be ideal. A further shortcoming is that an electrostatic dischargestructure (ESD) in series with the pin receiving the external resistoradds a variable amount of resistance in series with the externalresistor. This makes the selection of the external resistance subject tovariations in the ESD structure.

[0012] Further, a shortcoming in the technique of setting the current inthe slave is that a relatively complex algorithm between the slave andthe master is required to correctly set the current in the slave. Themaster sets the RC time constant which in turn determines the count andthe output value. The master then tests the output value to determinewhether it matches V_(ref). If not, it increases the count and reteststhe output value. This cycle continues until a match occurs. However, amatch of V_(out) to V_(ref) for one bus line, does not always insurethat a match will occur on another bus line due to small differences incharacteristics between output drivers, bus lines, and V_(ref)comparison circuits.

[0013] As can be seen, an improved output driver circuit and techniquesfor obtaining rapid switching speed with low power consumption and lownoise is needed.

SUMMARY OF THE INVENTION

[0014] The present invention includes a circuit and current controltechnique to enable high-speed buses with low noise. This circuitry maybe used in the interfacing of high-speed dynamic RAMs (DRAMs). Thearchitecture of the present invention includes the following components:an input isolation block (Isolation), an analog voltage divider (AVD),an input comparator, a sampling latch, a current control counter, and abitwise output driver (output driver A and output driver B).

[0015] A fundamental operation of the current control mechanism is toevaluate the voltage levels V_(hi), V_(low), and V_(ref), and incrementor decrement the current control counter accordingly to set anappropriate output level. When the current control circuitry is in anevaluation mode, output driver A is off (not sinking current), and nodeBDA is at the output high voltage level (typically V_(term)). Outputdriver B is active, and pulls node BDB to the low voltage output level.The voltage levels at nodes BDA and BDB are passed through the isolationblock, and fed into the analog voltage divider. The analog voltagedivider outputs a voltage level which is a weighted average of it'sinput. I.e., V_(out)=(A*V_(hi))+(B*V_(low)). For example, in a specificcase, V_(out)=(0.5*V_(hi))+(0.5*V_(low)).

[0016] The input comparator compares V_(out) and V_(ref) and generatesan up signal. The up signal is sampled, and used to increment ordecrement the current control value held in the current control counter.By repeating this process the current control value will settle to avalue where Vol=(V_(ref)−A*V_(term))/B.

[0017] When the current control circuitry is not active, the inputisolation block shields any interactions of the analog voltage dividercircuitry and the output pad.

[0018] The output driver is composed of a series of individual outputtransistors, an example of which is shown in FIG. 4. The number ofactive output transistor blocks are selected with control signalictrl[n:O]. The width of the output devices may be scaled in a geometricfashion to allow encoding of the ictrl[n:O] signal.

[0019] The input isolation gates may be implemented as CMOS pass gates,NMOS passgates with boosted gate voltages, unity gain buffers, oroperational amplifiers (op amps). The analog voltage divider may beimplemented with a resistor divider, a digital-to-analog converter, orswitched capacitor filter such as a sigma/delta modulator. The samplinglatch may be implemented as a simple flip-flop or latch, or a series ofsequential elements with logic to average the sampled value. The currentcontrol counter may be implemented as an up-down counter or a moresophisticated counter such as a saturating binary search counter.

[0020] Other objects, features, and advantages of the present inventionwill become apparent upon consideration of the following detaileddescription and the accompanying drawings, in which like referencedesignations represent like features throughout the figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 illustrates a prior art implementation of a current controlcircuit having a master device and slave device;

[0022]FIG. 2 shows a block diagram of current control circuitry inaccordance with an embodiment of the present invention;

[0023]FIG. 3 illustrates current control circuitry in accordance with anembodiment of the present invention;

[0024]FIG. 4 illustrates an output driver which may be utilized inaccordance with an embodiment of the invention;

[0025]FIG. 5 is a detailed illustration of an implementation of thecurrent control circuitry of the invention;

[0026]FIG. 6 shows circuitry for the gxCCbst1 element of FIG. 5, whichmay be used to generate a boosted voltage;

[0027]FIG. 7 shows circuitry for an input comparator gxCComp of FIG. 5;

[0028]FIG. 8 shows a resistor divider implementation for gxCCDiv0 ofFIG. 5; and

[0029]FIG. 9 shows a resistor divider implementation for gxCCDiv1 ofFIG. 5.

[0030]FIG. 10 illustrates control and test mode logic circuitry that maybe used in accordance with an embodiment of the invention.

[0031]FIG. 11 illustrates a current control counter circuit that may beused in accordance with an embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] The present invention provides an improved apparatus and methodof setting the current in master and slave devices connected to a commonbus. FIG. 1 is a block diagram of a current control implementation witha master device (RAC) and a slave device (RDRAM), in accordance with theprior art. FIG. 1 is simplified to display only a single slave deviceRDRAM, however it should be appreciated that many slave devices may beused in connection with the master device RAC.

[0033] In accordance with the prior art, the master device RAC has adedicated output pin CC. The output pin CC is connected to a terminationvoltage V_(term) through a resistor R_(term)/2. If the output driver isan ideal current source, then the voltage output will be the middle ofthe swing. This value is compared to V_(ref) and adjusted up or downaccordingly.

[0034] For the slave device RDRAM, there is a circuit that indirectlyinfers the amount to adjust the output current depending on variationsof voltage and temperature. The original proper value is established byrunning a current control initialization routine which requires readingdata back through the master device and detecting the first time validones are transmitted on the bus. This threshold is discovered and thendoubled (approximately) before being sent to the slave device.

[0035] The technique shown in FIG. 1 requires N+1 pins on the masterdevice, and N pins on the slave device. The additional pin on the masterdevice is required for the CC connection shown in FIG. 1. The device ofFIG. 1 also requires the resistor RT/2 on the printed circuit board uponwhich the master device is mounted. Unfortunately, the RT/2 resistor maynot have the desired value. The current produced by the outputtransistor varies slightly as the voltage changes, which means there arenon-ideal effects of the V−I characteristics of the output transistor,such as channel length modulation. So although it is desirable for thecurrent control resistor to be R_(term)/2, its value is more likelyabout R_(term)/2.2. The value also varies somewhat due to differences inprocess, vendor, and temperature.

[0036] Internal to the master device RAC, there is an input comparatorCOMP. The comparator compares V_(ref) to the voltage on the currentcontrol pin (CC). If the voltage comparison determines the output is toolow, then a counter (Counter3) is incremented, thereby increasing thecurrent of all the output drivers on the chip (during the next currentcontrol cycle). If the current is too high, then the counter (Counter3)is subsequently decreased. By selecting the proper resistor (which isdifficult to do), the current control circuit adjusts the output driveat regular intervals to keep the full voltage swing of the remainingpins. This then tracks any drift of the transistors due to voltage ortemperature effects, allows for different process variations chip tochip, and provides many similar benefits. However, selecting the properresistor value to achieve this result is difficult.

[0037] A further technique involves using an expansion mechanismreferred to as “y-channel.” However, this technique requires that theresistor value be changed (essentially halved) when the module isinserted, compared to the case when it is not inserted. This may beachieved by adding a parallel current control resistor to the one on themotherboard which essentially changes the parallel resistance so thatthe output current is doubled. Unfortunately, the nonlinear nature ofthe transistors again requires that a “special” resistor value becalculated in order to double the current. Once the proper resistorvalue is found, automatic tracking is still assured using the expansionmechanism.

[0038] A consideration that needs to be addressed for some integratedcircuits is that an electrostatic discharge (ESD) structure may beplaced in series with the current control pin. This adds a variableamount of resistance, significant enough to change the needed externalresistor value substantially. The resistance of such an ESD structureneeds to be accounted for.

[0039] As known in the art, current control calibrations are performedduring “quiet” times on the bus. That is, the current controlcalibrations are “scheduled” between activities on the bus.

[0040]FIG. 2 shows an overall diagram of an embodiment of the currentcontrol technique of the present invention. FIG. 3 is a schematic of thearchitecture utilized in accordance with the invention. FIGS. 4-8 showcircuit schematics of a specific implementation of the presentinvention.

[0041] The circuit of FIG. 2 includes the following components: an inputisolation block (Isolation) 120, an analog voltage divider (AVD) 104, aninput comparator 125, a sampling latch 130, a current control counter115, and a bitwise output driver (output driver A 107 and output driverB 111).

[0042] As shown in connection with FIG. 1, the prior art relied upon aninput comparator COMP in performing its current control functions. Thepresent invention also uses an input comparator 125 for current controlfunctions. However, unlike the prior art which received a controlvoltage from a dedicated external pin connected to a printed circuitboard mounted resistor RT/2, the present invention uses a simple R overR resistive divider placed between an active output and a nonactiveoutput. The output of the divider circuit is a voltage equal to(V_(term)−V_(swing))/2. This is exactly the value desired to compareagainst V_(ref). It is desirable that these two are equal. If they arenot, the current control circuit increments or decrements the counterand tracks any output current variations due to changes in current driveof the transistors (because of temperature or VDD changes).

[0043] The circuitry employs voltage divider circuitry 104 on both themaster and slave devices. As shown in FIG. 2, the voltage dividercircuitry is connected between bus drivers A and B, driver 107 and 111,respectively. This circuitry is activated when the operating currentmust be set in the bus drivers and deactivated when the bus drivers areused in normal operation.

[0044] Bus lines connected to the two selected drivers of the master aredifferent from bus lines connected to the two selected drivers of theslave device. Consequently, the setting of an operating value of currentin the master can proceed simultaneously with the setting of a value inthe slave. If there are multiple slaves, each slave device may use busdrivers connected to a unique pair of bus lines so that the setting ofthe operating current in the several slaves may proceed concurrently.Preferably, all slave devices use the same pins.

[0045] A counter (e.g., 115) in the master and in the slave determinesthe value of the current in the current driver as discussed above. Thecount in the master and slave is determined by a feedback circuit whichcompares a voltage reference, V_(ref), to a common node voltage,V_(out), which is derived from the voltage divider circuitry. Thefeedback circuit assures, via the counter, that V_(ref) is equal to[V_(term)−(V_(term)−V_(out))/(1+voltage divider ratio)] by adjustingcurrent in a selected one of the drivers to which the voltage dividercircuitry is connected. One of the drivers is left in the off condition,providing V_(term) to the voltage divider. Thus, the common mode voltageswings a fixed amount equal to (V_(term)−V_(ref)) which is appliedacross the upper one of the resistors, R1 (FIG. 3), of the voltagedivider when a resistive voltage divider is used. The lower one of theresistors, R2 (FIG. 3), has g*(V_(term)−V_(ref)) across it, where g isthe voltage divider ratio. I.e., g=R2/R1 where R1 is connected betweenthe off driver and the center node and R2 is connected between thecenter node and the on driver. Typical values for R1 and R2 areapproximately 10 K ohms. Thus, V_(out) , equals(1+g)*V_(ref)−g*V_(term). If the resistors are equal then g equals oneand V_(out) equals 2*V_(ref)−V_(term). For example, if V_(term) is 1.8volts and V_(ref) is 1.4 volts, then V_(out) is 1.0 volts and the swing,V_(swing), of V_(out) is 0.8 volts. Also, the current in the outputdriver is now V_(swing)/R_(term), which equals 0.8 volts/28=28.6milliamps. For example, R_(term) may be about 28 ohms. Typically,R_(term) may be in the range from about 20 ohms to about 50 ohms.

[0046] When the voltage divider circuit is activated, the circuit itselfcreates a source of voltage error, caused by the current that flowsthrough the voltage divider circuit from V_(term) through thetermination resistor, through R1 and R2 and to the output driver whichis in the on-state. This current causes the voltage of the driver in theoff-state to be slightly less than V_(term), say e*V_(term), where e isa number close to one. Specifically,e=I−[((V_(term)−V_(out))N_(term))*(R_(term)/(R1+R2+R_(term)))]. Thiscurrent also causes the voltage of the driver in the on-state to beslightly higher than V_(out) also by the same error term, saye*V_(term). Therefore, using the suggested resistor values, e=0.998882and V_(out)=1.002, so V_(out) has a 2 millivolt error.

[0047] The feedback circuit assures that the common node of the voltagedivider is locked to V_(ref), so that the drop across R1 is(e*V_(term)−V_(ref)). The voltage drop across R2 is e*V_(term)−V_(ref).The output voltage, V_(out), is 2*V_(ref)−e*V_(term). So the outputvoltage is slightly higher than its value in the absence of the voltagedivider. V_(swing) is now (1+e) V_(term)−2*V_(ref) and the current inthe output driver isV_(swing)/R_(term)+(V_(term)−e*V_(term))/R_(term)=2*(V_(term)−V_(ref))/R_(term)=30milliamps, as before. Thus, while the output voltage is altered slightlywhen the voltage divider circuit is activated, it does not affect thesetting of current in the output driver or the counter value thatcontrols that current.

[0048] Under ideal conditions the ratio of the resistors, g, is aprecise value, such as unity. However, if some errors are present in thecircuit, it is desirable to compensate for them by slightly altering theratio. Some sources of error are currents into the comparator andhysteresis or offsets in the comparator. Another source of error is thecircuitry used to activate the voltage divider circuitry, if theactivation circuitry is in the form of pass gates in series with R1 andR2 of the voltage divider.

[0049] Alternatively, the error current that flows in the dividercircuit may be negligible compared to the amount of current controlledby one half of the least significant bit of the counter, if theresistances in the divider can be made large enough. The value of(V_(term)−e*V_(term))R_(term) is approximately 0.15 milliamps. Theamount of current flowing through the voltage divider is[(V_(term)−V_(out))/(R1+R2+R_(term))] or typically about 0.04 mA. Sevenbits controlling 28.6 milliamps makes ½LSB equal to 0.11 milliamps.

[0050] Another reason for altering the ratio, g, is that the edge ratefor a rising signal may be different from a falling signal on the outputof the bus driver. Altering the voltage divider ratio so that the swingis not symmetric about V_(ref) may be necessary to obtain the best noisemargin for receiving the signal on the bus.

[0051] In one embodiment the relationship between the counter value andthe current in the driver is linear. Such a driver uses binary weightedoutput transistor legs to adjust the current in single steps from 0 to2^(N) where N is the number of current control bits. In otherembodiments there are other relationships between the counter value andcurrent in the driver. For example, a logarithmic relationship can beused. This allows more precision with smaller count values and lessprecision with larger count values.

[0052] In another embodiment, the counter counts up until the propercurrent is reached. After the initial setting, the counter counts up ordown to adjust the current in the driver. In another embodiment, morecomplex algorithms are employed to find the correct value for the count.One such algorithm is binary searching until a value close to thecorrect value is found and then counting up or down to obtain theprecise value.

[0053] In a further embodiment, the feedback and counter circuit settingapply to all of the bus drivers of a device. In another embodiment thereis a feedback and counter circuit for each or any number, 1-to-N, of thebus drivers of a device. This latter embodiment has the advantage thateach driver is correctly set, but the disadvantage that more circuitryis required.

[0054] The setting of operating current in the bus driver can consumetime on the bus, resulting in a loss of throughput. To eliminate thisloss, in one embodiment, the setting of the current occurs during aperiod of time on the bus which cannot be used otherwise. If the slavedevices are memory devices, that time is the time at which the memorydevices are refreshed, which typically occurs every 16 microseconds fora duration of 80 ns. In some cases the setting of the operating currentin the bus driver takes only about 20 ns, thus, the setting can occurconcurrently with the refresh operation.

[0055] Connected to the voltage divider circuitry is a means forcoupling the divider circuitry to the output lines to which it isattached. In one embodiment the means for coupling is simply a wireattached between the voltage divider circuitry and the output lines. Inan alternate embodiment the means for coupling is composed of a CMOSpass gate which serves to isolate the voltage divider circuitry from theoutput lines to which it is attached when the current control circuitryis not enabled In another embodiment the means of coupling is an NMOSpass gate with boosted gate voltages. A typical circuit to generate theboosted gate voltage level is shown in FIG. 6.

[0056] Other embodiments employ unity gain buffers, operationalamplifiers, transconductance, or sample-and hold circuitry to couple thevoltage at the output lines with the voltage divider. Still otherembodiments employ capacitors to couple a difference voltage from theoutput lines to the voltage divider, such as in some switched capacitorfilters.

[0057] While the above discussion referred to a resistance voltagedivider, other embodiments for dividers include the use of digital toanalog converters or switched capacitor filters such as a sigma/deltamodulator. An analog-to-digital converter may be used to convert theanalog input voltage and/or Vref values to a digital value. Subsequentdivision and comparison may then be performed by digital signalprocessing.

[0058] The output value from the voltage divider circuitry is comparedto a voltage reference value. The comparator may be a simple analogdifferential voltage comparator shown in FIG. 7. In an alternateembodiment, the comparator may be a regenerative sense-amp circuit. Thecomparator may also be a switched capacitor filter. In still anotherembodiment where an analog-to-digital converter is used as a voltagedivider, the comparator may be a digital signal processor.

[0059] Preferably, the reference voltage is provided from an externalpin. However, the reference voltage may also be generated with aband-gap reference circuit, or a voltage divider of Vdd or anothervoltage supply.

[0060] Preferably, two voltage divider ratios are selectable. Forexample, FIG. 5 illustrates two voltage divider devices 301 and 302 thatmay be alternately selected. The actual voltage divider circuits may beimplemented resistive ladders of the type shown in FIGS. 8 and 9.

[0061] In some embodiments, a sampling latch may be employed between theoutput of the comparator and the up-down counter. The sampling latchfunctions to average the output of the comparator so that the jitter onthe counter is reduced.

[0062] The invention does not require the CC pin and external resistorshown in the prior art device of FIG. 1. The invention also providesbetter tracking than the device of FIG. 1. For FIG. 1, a fairly complex,and somewhat unwieldy current control initialization algorithm isrequired to find the proper start value for each slave device. However,with the present invention, implementing the current control schemeeliminates the need for complex initialization as each slave deviceautomatically adjusts its own output to proper swing levels. Slavedevices are instructed on a regular but infrequent basis to check theoutputs. This may be accomplished during the same time a master deviceperforms its calibration.

[0063] For the master device, the benefits of the present inventioninclude the elimination of the CC pin and output driver and greateraccuracy of setting the proper current swing. Estimates show that byimplementing the current control technique of FIG. 2, an increase involtage margin yields about 70 MHz of additional timing margin.

[0064] Moreover, for the technique of the present invention, there is noneed for current control resistors on y-channel modules. However, thetechnique is also backwards compatible for modules that currently havesuch resistors.

[0065] Furthermore, the slave device automatically adjust its swing andmonitors the current to adjust for variations in output drive due tovoltage and temperature variations. Also, each slave device finds itsown current control value depending on the process variations of theindividual component.

[0066] The benefits of the present invention for the slave deviceinclude better swing accuracy (related to a similar benefit for themaster device), elimination of the existing current control trackinglogic in the slave device, and elimination of the current controlinitialization routine described in U.S. Pat. No. 5,254,883.

[0067] For the master device, two pins are used for current controladjustment. One pin is driven to a logic one (low voltage) and the otherpin is not driven. The time this is done is under control of the controllogic within the ASIC. The slave device is done at the same time, usingdifferent pins (for driving) than the master device is using. Duringthis operation, a resistive divider is inserted between two pins, usingpass transistors T1 and T2. These resistors halve the voltage betweenthem and compare against the V_(ref) voltage (already present on thechip). A counter is incremented if more current is needed to increasethe voltage swing or decremented if too much voltage swing is detected.Although the digital adjustment is a simple up/down counter, a moresophisticated binary search can be implemented, followed by a simpleadjust one up or down once the algorithm is completed. Such anembodiment is complicated, the savings of time to find the necessary setpoint may not justify elimination of a simple up/down counter.

[0068] For the slave device, two pins are used for current controladjustment. One pin is driven to a logic one (low voltage) and the otherpin is not driven. This is done using a special register read command(or this could be done during a memory refresh to the same device).During this operation, a resistive divider is inserted between two pins,using pass transistors T3 and T4. These resistors halve the voltagebetween them and compare against the V_(ref) voltage (already present onthe chip). A counter is incremented if more current is needed toincrease the voltage swing or decremented if too much voltage swing isdetected. Although the digital adjustment is a simple up/down counter, amore sophisticated binary search could have been implemented, followedby a simple adjust one up or down once the algorithm is completed.

[0069] The new method use two of the N total pins, different pins forthe master and the slave. During current calibration, one slave and themaster both calibrate at the same time, on different pins.

[0070]FIG. 10 illustrates control and test mode logic that may be usedin connection with the invention. The current control counter includesan adder 1030, a master latch 1031, a multiplexer 1032, a slave latch1033, random logic 1034, and a majority detector 1035. Using the controlcounter in FIG. 10, various modes of operations are possible. In a firstmode, the circuitry is placed in an “auto mode” when MD_sel Bypass 1016is asserted and MD_RD 1017 is asserted. In the auto mode,CCValue_ns[5:0] 1012 is coupled to CCValue_nsd[5:0] 1013. Each ccUpdate1020 pulse updates the current control value by one bit based on theValue IncrValue 1018 (which take values of 1, 0, or −1).

[0071] During initialization, a series of ccUpdate pulses will driveictrl[5:] 1014 to approach its equilibrium value. Periodic updates maybe done with subsequent ccUpdate pulses at specified intervals.

[0072] In a second mode, the circuitry is placed in a “manual mode” whenMD_sel Bypass 1016 is asserted and MD_RD 1017 is asserted. In the manualmode, CCValue_nsd[5:0] 1013 is coupled to CCreg[5:0] 1015. At the lowphase of ccUpdate, the value of ictrl[5:0] is loaded into CCReg[5:0]1015. This mode may be used to drive an arbitrary ictrl[5:0] value, orto preload the master-slave flip flop (1033) before entering Auto mode.The same datapath is used during the Direct Access Test mode where testvalues of ictrl[5:0] are driven by changing CCReg[5:0]. A “mid” value ofCCValue[5:0]=100000 may be preloaded at initialization so theequilibrium value is reached with fewer numbers of ccUpdate pulses.

[0073] The circuitry may also be placed in a “force mode” when MD_RD1017 is de-asserted. In the force mode, a specific value may be forcedat ictrl[5:0] when MD_RD 1017 is de-asserted. In the preferredembodiment, random logic forces ictrl[5:0]=101111. An alternateembodiment may implement a different forced value or values. This modeis used for testing and calibration.

[0074] The majority detector filters the value of CCIncr 1019 andprevents toggling of ictrl[5:0] when the value is within one bit of thesettled value. The majority detector takes an even number of samples ofSignal CCIncr. The IncrValue 1018 is “1” if the majority of samples arehigh The IncrValue 1018 is “−1” if the majority of samples are low. TheIncrValue 1018 is “0” if there is no majority.

[0075]FIG. 11 shows another embodiment of current control counter thatmay be used in accordance with the invention This implementation uses aseven-bit ictrl value. The circuitry 1100 has three modes of operation.In a first mode, the circuitry is placed in an “auto-acquire mode” whenCCtlEn is high and CCtlAuto is high. In the auto-acquire mode, theup-down counter is coupled to ictrl[6:0]. As the up-down counter isincremented or decremented, ictrl[6:0] is changed accordingly, until theequilibrium value of ictrl[6:0] is reached. At this point, theequilibrium value is loaded into CCR with signal CCtlLd, and the currentcontrol counter may enter Auto mode.

[0076] The circuitry may also be placed in an “auto mode” when CCtlEn islow and CCtlAuto is high. In the auto mode, the register in the CCRblock controls the current setting of ictrl[6:0]. In this mode, theup-down counter is also coupled to the CCR register.

[0077] The circuitry also has a “manual mode” when CCtlEn is low andCCtlAuto is low. In the manual mode, a seven-bit value CCtl[6:0] isdriven or stored into the counter and ictrl[6:0]. This mode is used toset a value into the counter and register that is close to the settingthat will actually result in the auto-acquire mode, which cuts down onthe time it takes to reach the equilibrium ictrl[6:0] value. This modemay also be used to set the counter and register to a certain valuebefore the auto-acquire mode is entered. This mode may also be used as atest or direct access mode where specific values may be driven ontoicrtl[6:0] by changing Cctl[6:0].

[0078] The current control circuitry may be implemented with a singleoutput pin to perform current calibration. Both “high” and “low” voltagevalues are measured from the same pin sequentially with sample-and-holdcircuitry. Subsequent processing of these voltage values are averagedwith a voltage divider.

[0079] In another embodiment, the pin voltage values are measured duringnormal operation of the RDRAM. Based on data of the DRAM “read”operations, the current control circuitry determines when stable output“high” or “low” voltage patterns are present on the pin. A single pin ormultiple pins may be used to measure the pad voltage. Multiple samplesand averaging may be performed to filter noise coupling and reflectionon the output channel from the stable output “high” and “low” levels.This embodiment has the advantage of requiring no “quiet period” on thechannel for current control calibration.

[0080] The foregoing description, for purposes of explanation, usedspecific nomenclature to provide a thorough understanding of theinvention. However, it will be apparent to one skilled in the art thatthe specific details are not required in order to practice theinvention. In other instances, well known circuits and devices are shownin block diagram form in order to avoid unnecessary distraction from theunderlying invention. Thus, the foregoing descriptions of specificembodiments of the present invention are presented for purposes ofillustration and description. They are not intended to be exhaustive orto limit the invention to the precise forms disclosed, obviously manymodifications and variations are possible in view of the aboveteachings. The embodiments were chosen and described in order to bestexplain the principles of the invention and its practical applications,to thereby enable others skilled in the art to best utilize theinvention and various embodiments with various modifications as aresuited to the particular use contemplated. It is intended that the scopeof the invention be defined by the following claims and theirequivalents.

What is claimed is:
 1. A circuit for controlling signal levels on atransmission channel, comprising: a voltage divider to output an averageof its inputs; a first output driver connected to a first input of thevoltage divider; a second output driver connected to a second input ofthe voltage divider; an input comparator to compare the output of thevoltage divider with a reference voltage; a latch to sample an output ofthe input comparator; a current control counter holding a currentcontrol value, adjusted based on a content of the latch, wherein thecurrent control counter determines output levels at an output of theintegrated circuit.
 2. The circuit of claim 1 further comprising: anisolation block to shield interaction between the voltage divider and anoutput pad during a period when current levels are not being evaluatedat the output of the integrated circuit.
 3. The circuit of claim 1wherein the current control counter is an up/down counter.
 4. A circuitfor controlling signal levels on a transmission channel, comprising: acomparator with a reference voltage input node, a current controlvoltage input node, and an output node; a voltage divider with a firstinput node connected to a termination resistor node, a second input nodeconnected to said termination resistor node, and an output nodeconnected to said current control voltage input node; a first outputdriver circuit connected to said first input node to control the valuethereon; a second output driver circuit connected to said second inputnode to control the value thereon; and a current control circuitconnected to said comparator output node, said current control circuitcontrolling signal levels on a transmission channel in response to anoutput signal from said comparator.
 5. The circuit of claim 4 whereinsaid current control circuit is an up/down counter.
 6. A circuit forcontrolling the operating current of an output driver, comprising: afirst adjustable output driver responsive to a current setting inputsignal; a second adjustable output driver responsive to said currentsetting input signal; a first load element with one end coupled to atermination voltage and a second end coupled to said first adjustableoutput driver; a second load element with one end coupled to atermination voltage and a second end coupled to said second adjustableoutput driver; a voltage divider with a first input node, a second inputnode, and a common node, said common node providing an output voltagebased upon signals received at said first input node and said secondinput node; a first signal link between said first input node and saidfirst adjustable output driver; a second signal link between said secondinput node and said second adjustable output driver; a comparator toproduce a comparator output signal based upon a reference voltage andsaid output voltage from said voltage divider; and a counter to generatesaid current setting input signal in response to said comparator outputsignal, such that said output voltage of said voltage divider issubstantially the same as said reference voltage.
 7. The circuit ofclaim 6 further comprising a latch to store the comparator output signalduring normal operation.
 8. The circuit of claim 6 further comprising acombinational and sequential logic circuit to filter said comparatoroutput signal.
 9. The circuit of claim 6 wherein said counter is anup/down counter.
 10. The circuit of claim 6 further comprising atime-multiplexed common pin coupled to said first adjustable outputdriver, said second adjustable output driver, said first load element,and said second load element.
 11. The circuit of claim 6 wherein saidfirst load element and said second load element are each a linearresistor.
 12. The circuit of claim 6 wherein said first load element andsaid second load element are each a non-linear device.
 13. The circuitof claim 6 wherein said first output driver comprises a plurality oftransistors of preselected widths arranged in a geometric manner. 14.The circuit of claim 6 wherein said first output driver comprises aplurality of transistors of preselected widths arranged in a logarithmicmanner.
 15. The circuit of claim 6 wherein said first output drivercomprises a plurality of transistors of preselected widths arranged inlinear manner.
 16. The circuit of claim 6 wherein said first outputdriver comprises a plurality of transistors of preselected widthsarranged in non-linear manner.
 17. The circuit of claim 6 wherein saidvoltage divider is a resistive ladder.
 18. The circuit of claim 6wherein said voltage divider has selectable divide ratios.
 19. Thecircuit of claim 6 wherein said voltage divider is a digital-to-analogconverter.
 20. The circuit of claim 6 wherein said voltage divider is aswitched capacitor processor.
 21. The circuit of claim 6 wherein saidvoltage divider is a digital signal processor.
 22. The circuit of claim6 wherein said voltage divider is a resistive ladder.
 23. The circuit ofclaim 6 wherein said first signal link and said second signal link areeach a wire.
 24. The circuit of claim 6 wherein said first signal linkand said second signal link are each a semiconductor pass gate.
 25. Thecircuit of claim 6 wherein said first signal link and said second signallink are each an operational amplifier buffer.
 26. The circuit of claim6 wherein said first signal link and said second signal link are each ananalog-to-digital converter.
 27. The circuit of claim 6 wherein saidfirst signal link and said second signal link are each a capacitor. 28.The circuit of claim 6 wherein said first signal link and said secondsignal link are each a sample-and-hold circuit.
 29. The circuit of claim6 wherein said comparator is an analog comparator.
 30. The circuit ofclaim 6 wherein said comparator is a digital signal processor.
 31. Thecircuit of claim 6 wherein said first adjustable output driver, saidsecond adjustable output driver, said first load element, said secondload element, said voltage divider, said first signal link, said secondsignal link, said comparator, and said counter are positioned in asingle package.
 32. The circuit of claim 6 wherein said first adjustableoutput driver, said second adjustable output driver, said first loadelement, said second load element, said voltage divider, said firstsignal link, said second signal link, and said comparator are positionedin a first package and said counter is positioned in a second package.33. The circuit of claim 6 wherein said first adjustable output driver,said second adjustable output driver, said first load element, saidsecond load element, said first signal link, and said second signal linkare positioned in a first package and said voltage divider and saidcounter are positioned in a second package.
 34. A method of establishingan operating current for an output driver, said method comprising thesteps of: coupling a voltage divider between two adjustable outputdrivers, wherein the first output driver is in an on state and thesecond is in an off state, and an output of each output driver iscoupled to one side of a termination load device, while the other sideof each termination load device is coupled to a termination voltage;comparing a common node of said voltage divider to a reference voltage;and adjusting the count value of a counter in response to said comparingstep until said common node of said voltage divider is substantially thesame as said reference voltage.